The present application relates to semiconductor technology, and more particularly to a method of forming a semiconductor structure containing a tensile strained high germanium content silicon germanium alloy fin portion located on an insulator layer and surrounded by a doped silicon germanium alloy source/drain structure having a germanium content that is less than that of the silicon germanium alloy fin portion. The present application also relates to a semiconductor structure that is formed by the method of the present application.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor FinFETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Silicon germanium alloy fins having from 25 atomic percent to 85 atomic percent germanium are front-up options for 10 nm and beyond technologies. Silicon germanium alloy fins having from 25 atomic percent to 50 atomic percent germanium are options only for 10 nm pFET devices. However, 7 nm technology is looking for silicon germanium alloy fins for both nFET and pFET devices. In some instances (for cost savings and easy processing), it is preferred to use the same channel material for both nFET and pFET devices. To gain the most out of the pFET device, the silicon germanium alloy has to have a high germanium content. Silicon germanium alloys having a high germanium percentage are not generally suitable for nFET devices. As such, there is a need for providing a method and structure in which silicon germanium alloy fins having a high germanium content can be used for both nFET and pFET devices.